Information present in technology files,design spec and information from top level engineer(physical design flow).

• Cell delays and there output slews based on different PVT conditions.
• Height of Standard cells.
•  Resistance, Capacitance of metal layers.
•  Die size.
•  Core Area.
•  Ports info,
•  Scan chain Information.
• Technology used.
•  widths and spacing of metal layers. 
• Area of the standard cells and Macros.
• Static leakage currents of the standard cells
• Threshold voltage of the standard cells.
•  Macros netlsit's.(from vendors)
• Macros blockages information.
• SDC file