Information present in technology files,design spec and information from top level engineer(physical design flow).

• Cell delays and there output slews based on different PVT conditions.
• Height of Standard cells.
•  Resistance, Capacitance of metal layers.
•  Die size.
•  Core Area.
•  Ports info,
•  Scan chain Information.
• Technology used.
•  widths and spacing of metal layers. 
• Area of the standard cells and Macros.
• Static leakage currents of the standard cells
• Threshold voltage of the standard cells.
•  Macros netlsit's.(from vendors)
• Macros blockages information.
• SDC file

TARGETS FOR PHYSICAL DESIGN/APR FLOW

• Targets of Floorplan

1. Stack the macros so that there is contagious space for Standard cells.
2. Entire design depends on quality of the floorplan.
3. Meet IR Drop as per specification.
4. Distribute the power all over the chip with minimum metal usage.

•  Targets of Placement

1. Design should be routable,Meet timing.
2. Reduce congestion,place blockages to avoid floating metals & wrong placement of standard cells.
3. Scan chain reordering 

• Targets of CTS

1. To meet signal transition, capacitance.
2. Meeting Global skew
3. Max fanout.
4. Clock domine buffer crossing.
5. Checking hold slack.

• Targets of Routing

1. Performing clock & signal routing with minimum metal jogging considering size of G-cell.

APR FLOW TCL SCRIPTS

1. SUMMARY:

The solo purpose for preparing the TCL scripts for APR flow is to automate the design process and scripts have to be generic such that for any new incoming projects these scripts should be handy with minimum considerable changes.

2. BACKGROUND:

In physical design before starting to script the flow it’s important that one should be familiar with the inputs required and how the tool is modeled to understand these inputs.

In soc encounter all the inputs are set to variables and these variables should be invoked through the script when they are needed.

When we say that script is generic that means the script will is capable of doing the following for any design with few changes,

1. Stating designs (importing) – allows you to specify data for starting or initializing a design.
2. Saving designs – capable of saving the intermediate work completed on designs for accessing it later.
3. Restoring designs – allowing to load the saved data from a previous session.
4. Loading design data – to load design data saved in various stages of the design process, and to bring data from specific formats(DEF, PDEF, OA, Cellview, SDF) into the EDI

3. DETAILS:

Till today we completed developing script for loading the design and working with floorplan and power analysis. Please go through following directory

/ether_pnr/ether/scripts/

Loading the design:

We have broken the design loading process as follows,

1.    First, one have to load the common_setup.tcl

2.    Next stage is to load the design_setup.tcl   

Common_setup.tcl

This script is to set all the required variables and whenever a new encounter is logged in this script should be sourced. This script is not generic its design depended, for any new incoming designs this scripts has to be reviewed. Basically this script contains all the variables present in all APR scripts. By writing this script we are actually making all other APR scripts very generic.

Design_setup.tcl

                This script is very generic it can be used for any new incoming designs. After sourcing this script design will be loaded successful.  

Floorplan script (floorplan.tcl)

Floorplanning the design is done in steps as follows,

1.    Floorplan – fixing the values like utilization, aspect ratio, fixing core to IO area i.e clearance area.

2.    Power plan.